1. Field of the Invention
The present invention relates to a computing system, and, more particularly, to an improved high speed computing system which is capable of accessing split line data located on the border of two pages within one cycle on a cache read operation through the use of an improved configuration containing a prefetcher, a translational lookaside buffer(TLB) and a cache memory.
2. Description of the Prior Art
A computer system generally employs a memory management unit (MMU) and a cache memory in order to obtain a high performance operation thereof.
Referring to FIG. 1, there is shown a block diagram of a conventional computing system. The computing system includes a prefetcher 11, a translation lookaside buffer (TLB) 12, a page unit 13, a code/data cache memory 14, a bus unit 15, a prefetcher queue 16, an execution unit 17, an aligner 18, a x-pairing checker 19, a y-pairing checker 20, and a decode control unit 21. The prefetcher 11 generates a linear address (LA[31:0]) used in the access of code/data cache memory 14 when an access request signal is received from execution unit 17 and the like. The lower 12-bits (LA[11:0]) of the linear address are relayed to the code/data cache memory 14 because the prefetcher does not carry out an address translation and the upper 20-bits (LA[31:12]) are outputted to TLB 12 and page unit 13 in order to perform an address conversion.
The page unit 13 carries out control of an address translation by receiving the linear address (LA[31:12]) from the prefetcher 11 and a hit signal (TBLhit) from TLB 12. The page unit 13 also outputs a request signal (TWALK[31:2]) for a main memory access to bus unit 15 in order to obtain information for an address translation from a main memory (not shown) when the address translation fails in TLB 12 (a hit signal is not issued).
The TLB 12 stores the information needed to do an address translation and outputs a TLB hit signal to page unit 13 and a translated physical address (PA[31:12]) to code/data cache memory 14 by translating the upper 20-bits (LA[31:12]) of the linear address generated from prefetcher 11 into a physical address.
The code/data cache memory 14 stores instructions to be applied to the prefetcher queue 16 (in the case of a code cache) and to the execution unit 17 (in the case of a data cache); and receives the addresses from prefetcher 11 and the TLB 12 to load a line instruction(32 byte) on the prefetcher queue 16 or the execution unit 17.
There is a 64-bit path to load directly in bus unit 15 to reduce lowering of performance of the computing system as much as possible when an input of an instruction to the decode control unit 21 is interrupted due to an access missing the code/data cache memory 14.
At the decode control unit 21, the instruction is decoded by reading the instruction from the prefetch queue 16 through the aligner 18, if it is necessary. There are two paths directing to the x-pairing and the y-pairing checkers 19 and 20 from a queue pair 0 and 1 to support a dual pipeline.
In the x- and the y-pairing checkers 19 and 20, a possibility of the pairing is determined and informed to prefetcher 11.
As described above, in a general computing system, a translation lookaside buffer (TLB) is used to reduce the times of access to main memory when the system tries to access a main memory after an address translation. An upper address is translated by using translation lookaside buffer (TLB), and, next, compared with a tag of the data/code cache memory by an access to the cache memory. When a prefetch is executed for a spilt line or when a data to be read is located on the border of two pages during an access to the cache memory, the translation lookaside buffer (TLB) should be accessed two times to get a physical address from a first page and a second page.
Consequently, there is a problem of lowering of performance of the conventional computing system which uses an single-port translation lookaside buffer (TLB) and a cache memory because the translation lookaside buffer (TLB) is accessed at least two times and also the cache memory is accessed 2 times when an access to the split line on the border of two pages is carried out.